Altera Forums

CAM the hard way or how to compare against thousands of bits?

Yocto — Mon, 21 May 2012 02:55:32 GMT

Guys,

I don't have a lot of experience with FPGAs and so I turn to you my friends for an advice. The circuit I am aiming to create is relative simple, but I am not sure about what is the right way to do it.

The module should get data off of the Avalon-MM FIFO, 32-bit wide. Let's think in software terms and call those 32-bits an unsigned integer. That integer must be compared against a pre-configured list of numbers, approx. 5000 of them (5K * 32 bits = 19.53125 kilobytes). The output should be two things:

1) A signal that is positive if there was a match, or negative otherwise.
2) If the output is positive, the offset of the matching register (i.e. register address) should be stored in [31:0] register value.

(of course there will also be a simple reset logic)

I am thinking to use on-chip memory as 19KByte doesn't seem like a big deal, and create a module where a number of 32-bit registers will be a parameter. Those registers will be exported to a on-chip CPU, where software would write some data into it (HAL + uCOS).

Does this sound as a good idea thus far? Now, I can think about two ways to go from here to compare that number against value in registers:

Way #1, something like:

[code]
for (i = 0; i < MAX_REGS_PARAMETER; ++i)
begin
if (input_data[31:0] == reg[31 + (i * ...):(i * ...)])
output_signal <= 1'b1;
end
[code]

...

Way #2, generated combinatorial:

[code]
assign output_signal = (input_data[31:0] == reg1[31:0]) || (input_data[31:0] == reg2[31:00]) ....
[code]

I am not sure about how that code will synthesize and how big of a delay this comparison will introduce. Will that comparison take long and does it make sense to pipeline or no?

Which way do you think is better and why? Or is there any other way to do a thing like that? How would you do it? Your help is very much appreciated.

Thank you very much,
V.

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Getting Started With Quartus II Software - Not responding

jb777 — Mon, 21 May 2012 02:13:39 GMT

Hi all, new to this forum.

I'm running Quartus II Web Edition 11.1 SP2 on Ubuntu 12.04. When launched it displays the "Getting Started With Quartus II Software" splash/dialog screen. It does not allow me to select any of the elements e.g. buttons, previous opened projects, hyper links and close button by using either the left mouse button or enter key.

I previously had installed 11.1 SP1 and Ubuntu 11.10, and Quartus behaved OK.

Any suggestions welcome.

Jim

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modelsim10.0 can't Loading bytestream_pli.dll

jhljs — Mon, 21 May 2012 00:58:20 GMT

# Loading ./..//submodules/bytestream_pli.dll
# ** Error: (vsim-3193) Load of "./..//submodules/bytestream_pli.dll" failed: Bad DLL format.
# ** Error: (vsim-PLI-3002) Failed to load PLI object file "./..//submodules/bytestream_pli.dll".

There any ready code for using the 5 Mega Pixel Digital Camera Package

cfronza — Sun, 20 May 2012 21:51:40 GMT

I want to if exists any ready example code for use the camera function?
thanks

LOC Program for VHDL

koko — Sun, 20 May 2012 21:47:10 GMT

Hey Guys. I've been asked to count the number of lines of code (LOC) for VHDL. I need to count the physicial lines of code, logical lines of code, and also the number of commented lines.

Anyone have any ideas on an algorithm I can use for this?

DE0 or DE0-Nano for image processing study

OctalByte — Sun, 20 May 2012 19:58:49 GMT

Hello, I am an undergraduate student in Computer Engineering and I'm in need of a little advice.

I'm starting to learn about image processing because in the future I would like to create a device with some machine vision capabilities (edge detection, etc) as a senior design project; however, for now I'm looking for an FPGA I can use over the summer to tinker with and learn about creating and sending images to a monitor in the first place. I've narrowed down my prospects to either the DE0 or DE0-nano. That the DE0 has a vga port already on it would have made the choice obvious, but I found a site where someone was able to make a very simple vga breakout board for the Nano; that coupled with its Cyclone IV and that its all around more powerful has put me on the fence.

For what I'm doing, the end goal being to learn what I can about elementary image processing, should I buy a DE0 or DE0-Nano? Money is not factor.

Thanks :)

SIGSEGV in ModelSim 10.0c

josyb — Sun, 20 May 2012 18:51:59 GMT

I get the following error doing RTL simulation in ModelSim

Quote:

# Loading work.ple(a)
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Process: /iddreaderbinning_vhd_tst/i1/line__195 File: C:/qdesigns/c-cam/cameras/sensor/cmosis/cmvremap/cmvremapbinning/iddreaderbinning/iddreaderbinning.vhd
# FATAL ERROR while loading design
# Error loading design

The offending line is in bold:

Code:

begin



        process(Clk, Reset) is

                begin

                        if Reset = '1' then

                                oddline <= '0';

                                Q        <= (others => '0') ;

                                muxsel <= 0 ;

                                

                        elsif rising_edge(Clk) then

                                if (StartOfFrame = '1') or (EndOfLine = '1') then

                                        oddline <= (not StartOfFrame) and (not oddline) ;

                                end if;

                                

                                if (pl_Ena(0) = '1') then

                                        Q <= subvector( std_logic_vector(

                                                 to_unsigned( 

                                                                ( to_integer( unsigned( subvector(ramreader_Q , WIDTH_D * 1 - 1 , WIDTH_D * 0 ))) 

                                                                + to_integer( unsigned( subvector(ramreader_Q , WIDTH_D * 2 - 1 , WIDTH_D * 1 ))))

                                                        +        ( to_integer( unsigned( subvector(ramreader_Q , WIDTH_D * 3 - 1 , WIDTH_D * 2 ))) 

                                                                + to_integer( unsigned( subvector(ramreader_Q , WIDTH_D * 4 - 1 , WIDTH_D * 3 )))) , 

                                                        WIDTH_D + 2)) , 

                                                        WIDTH_D + 2 - 1 , WIDTH_D - WIDTH_Q + 2 ) ;

                                end if ;

                                

                                muxsel <= to_integer( unsigned( subvector( ramreader_A , ADDRESS_WIDTH , ADDRESS_WIDTH - 1 ))) ;

        

                        end if;

                end process ;

                

                

        process(EndOfLine , oddline , YHeight , D , rowcounter_Q , ramreader_A , muxeven_Q , muxodd_Q , ramreader_EoP , ramreader_RdAvail , pl_WrFree)

                        variable rowcounterqslv : std_logic_vector(WIDTH_ROWCOUNT - 1 downto 0) ;

                begin

                

                        ramreaderstartp <= EndOfLine and oddline;

        

                        rowcountermax <= to_integer( unsigned( YHeight)) ;

        

                        muxevend <= subset_stdlogic_2D( D , 3 , 0 ) ;

                        muxoddd  <= subset_stdlogic_2D( D , 7 , 4 ) ;

                        

                        rowcounterqslv := std_logic_vector( to_unsigned( rowcounter_Q ,  WIDTH_ROWCOUNT )) ;

                        A <= combine_slv( rowcounterqslv(0) , subvector(ramreader_A , ADDRESS_WIDTH - 2  , 0)) ;

                        

                        ramreaderdata <= combine_slv( muxodd_Q , muxeven_Q ) ;

                        rowcountercnten <= ramreader_EoP and ramreader_RdAvail and pl_WrFree ;

                end process;





        rowcounter : upcounter

                generic map(

Any suggestions ?

Using FPGA code in mobile phones to speed up processors

dude434 — Sun, 20 May 2012 15:01:35 GMT

How can one use FPGA code in mobile phones to speed up processors?
I have a iphone & android HTC but they are very slow in processing therefore if there is an app to increase or by pass the processor normal memory usage it would really make life easier? Any help appreciated?

TSE with SGDMA Busy problem

shmueld — Sun, 20 May 2012 14:42:20 GMT

I have a system with 2 CPUs. I have a working system where I have connected up a TSE to 2 seperate SGDMAs (Rx & Tx) and 2 seperate memories (Rx & Tx) which is controlled by the first CPU.

We needed to modify the system such the 2nd CPU now controls the system system. All I did is I changed the connections of the first CPU to the memories, SGDMAs and TSE and replaced them with the 2nd CPU. When we tried to trasnfer data via a loopback (as we had successfully done in the first system) all the data appears to have been sent, received and actually copied correctly to the Rx memory. The problem is that the SGDAM busy bit is not clearing.

Can anyone help me and give some direction of where to look ? The software engineer that I am working with has told me he is using exactly the same code as he used for the first system and he thinks has made the appropriate changes to the initialization code.

Could Accelerometer on DE0 NANO can communicate in I2C

linww — Sat, 19 May 2012 18:20:45 GMT

HI,I have a de0 nano,and i description the I2C in VHDL by myself.as http://wenku.baidu.com/view/4a4240ee...cfad6b8b5.html it`s OK work on AT24C02
.Now I like have a try on Accelerometer,but I want`t to communication with SPI,because I haven`t description SPI before,if the program is wrong i can`t sure is the SPI work abnormaly or set the Accelerometer in wrong.
SO could you tell me,can I communication with the Accelerometer in I2C,on DE0 NANO? THANKS A LOT!:-P

assembly inline C for NIOS II

zhoushanjinjie — Sat, 19 May 2012 10:18:06 GMT

Hi all,

I am new for NIOS II application develoment.
And I need to embed a few lines of assembly
in my C code. like:

#include "system.h"

void main()
{
C code 1;
_asm_("assembly 1");
C code 2;
_asm_("assembly 2");
C code 3;
}

My question is if the Nios II SBT will automatically
save the previous operation results (from registers
or somewhere else) before execute the assembly.
As we know it does when the system handle interrupt.
But how about this sutiation? Thanks in advance if you can help.:)

Jay

Usermode

ptangella42 — Fri, 18 May 2012 20:37:37 GMT

Can anyone please tell me the procedure for entering the usermode, in order to see the status of the CRC_ERROR pin in cycloneii EP2C35.

Thank you in advance

Arria II GX and SDI-HSMC Daughter card

tsprinkle — Fri, 18 May 2012 20:34:33 GMT

Can anyone point me in the right direction or give me some information about developing with the Arria II GX Development Kit and the SDI-HSMC Daughter card? Every thing I see on the internet has the Stratix IV board using the SDI-HSMC daughter card and the DVI-HSMC daughter card with the Arria II board.

Thanks,

Taylor

Verilog Synthesis Q

MarkEverly — Fri, 18 May 2012 20:29:10 GMT

Am bumping into a synthesis problem inside of an always construct. Simplified code is

reg true_or_false[0:9999];
reg a;

always (negedge clk)
begin
if (a <5000)
true_or_false[a] <= 1
else if (a < 10000)
true_or_false[a+5000] <= 1
end

The error I get is "Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in device....."

If I remove the if else construct, no allocations (register/memory/etc) are > 30%.

I'm quite sure I'm violating an HDL paradigm. Could use a little guidance on why and thoughts on how I might implement it correctly.

THNX,
ME

Help starting out with Arria II GX Dev Board and SDI HSMC Daughter card

tsprinkle — Fri, 18 May 2012 20:09:12 GMT

mSGDMA with different write clock and read clocks

eldos — Fri, 18 May 2012 17:44:20 GMT

Hi,

I am using the modular SGDMA (mSGDMA) with the PCIe connected to DDR memories. NIOS processor programs the descriptors. I would like to use different clocks for descriptor programming, for read side and for write side. Is this possible without modifying the mSGDMA source code?

Thanks!

Terasic DE2-115 flash elf

MarkEverly — Fri, 18 May 2012 17:37:10 GMT

Am using Quartus/Eclipse with DE2-115. Can someone provide some guidance on how to compile NIOS based application developed under eclipse so it can be falshed as opposed to loading through the debugger each execution.

Thnx
ME

Terasic DE2-115 Flash programming

MarkEverly — Fri, 18 May 2012 17:24:48 GMT